The present invention relates to the intra-system architecture of peripheral devices and multifunction peripheral devices and, more particularly, to the modularization of such architecture to take advantage of packet-switched interconnect technology.
The intra-system architectures of peripheral devices such as printers, scanners, copiers, and fax machines, or multifunction peripheral (MFP) devices which combine two or more peripheral devices into a single device, have conventionally been designed with an emphasis toward the integration of functions or systems. Thus, an MFP device having both printing and scanning capabilities typically includes as part of its intra-system architecture, an application specific integrated circuit (ASIC) which is designed to perform the functions of both the printer system and the scanner system. In addition to the printer and scanner systems, other systems such as the input-output (1I) system and a processor core may also be integrated into the single ASIC chip.
Several factors have traditionally encouraged the use of highly integrated ASICs in MFP and printer architectures. One such factor is cost. By integrating many systems or circuits onto a single ASIC chip, various pins are shared among systems which reduces the overall pin-count required to implement all of the systems, thereby reducing the cost. Furthermore, as higher volumes of a particular ASIC are produced and used in a product, the cost for each ASIC drops, thereby reducing the overall product cost.
Another factor that has encouraged the use of more highly integrated ASICs in MFP and printer architectures is interconnect technology performance. The chip-to-chip and backplane interconnect technology traditionally used in MFP and printer architectures has been the PCI (peripheral component interface) bus. PCI bus architectures typically have a hierarchy of shared multi-drop buses which rely on address broadcasting to alert target systems of a transaction, thus limiting communications over the bus to one system at a time. System components are plugged into the bus according to their required performance levels, with low performance systems being plugged into lower performance buses that are bridged to higher performance buses so as to not burden higher performance systems.
Shared multi-drop buses have recently begun to reach their full performance potential, and techniques such as increasing bus frequency and widening the bus interface have been applied to gain higher levels of bus throughput. As bus frequency and width increase however, the ability to have more than a few systems attached to a shared bus becomes a difficult design challenge due to the corresponding need to reduce the number of electrical loads (e.g., systems) on a single bus. This challenge has in turn encouraged a higher level of system integration onto ASIC chips. Therefore, both product cost and the state of system interconnect technology have tended to support the use of more highly integrated ASICs in MFP and printer architectures.
Unfortunately, there can be significant disadvantages to using more highly integrated ASICs in the design of printer and MFP devices. Generally, ASICs that are highly integrated require higher development costs when they are newly designed or redesigned, are not leveragable across products, and increase the time to market for new products. These disadvantages are more pronounced in a market environment increasingly driven by rapid technological innovation. Time to market for a new peripheral device is key to its success, and rapid technological innovation drives the need to quickly release new products to the market in order to capture the benefits of new technology. In such an environment, highly integrated ASICs, limited to use in specific peripheral products, create a significant bottleneck in the development of newly designed peripheral devices.
For example, an MFP device having printer and scanner functions may be redesigned to integrate a fax function as well. This change would seemingly only require the effort of integrating a fax system onto a prior ASIC which already includes a printer and scanner system. However, each time an ASIC is redesigned to alter one of its integrated systems or to add a new system, every system on the ASIC must be reverified to ensure that a bug or architectural flaw has not been introduced in the process. This process is costly, since ASIC development involves the separate work of hardware and software engineers, with the software engineers having to wait for the first silicon to become available from an ASIC design before implementing code to test and verify the different systems integrated onto the ASIC. Therefore, the need to quickly turn new technology into a peripheral product and release it to market is very difficult to meet when highly integrated ASICs, limited to use in specific peripheral products, are being used in new peripheral product designs.
Finally, the use of highly integrated ASICs in intra-system architectures does not exploit the potential advantages that immerging packet-switched interconnect technologies can provide. In general, systems in peripheral devices such as printers, scanners, and fax machines are increasingly required to handle higher volumes of information as colors are used, resolutions are increased, more electronic equipment is digitalized, and general networking environments progress. For example, a printer was once the output device connected to a host computer. Today, a printer can directly output data from a scanner and digital camera without using a host computer.
Therefore, to support the higher performance demands of peripheral devices, system interconnect buses must carry much higher volumes of information. However, conventional shared multi-drop PCI bus technologies have begun to reach their full potential over the past number of years, as mentioned above, and new, high performance packet-switched interconnect technology is available. Packet-switched interconnect technology allows point-to-point, moderately parallel interconnects through a switch fabric that permits a flattened (rather than hierarchical) architecture that uses fewer interface pins while providing greater transmission distance, lower transaction latency, and higher bandwidth.
Thus, where performance limited PCI hierarchical shared bus architectures benefit from the use of highly integrated ASICs, the enhanced performance and reduced pin count per interface available with packet-switched interconnect technology diminishes the need for highly integrated system architectures.
Modularized intra-system architectures for printer and multifunction peripheral (MFP) devices are based on disintegrating traditionally highly integrated systems into separate system components which incorporate immerging packet-switched interconnect technologies. Where the performance levels of conventional shared multi-drop bus architectures using more highly integrated systems have peaked, the modularized MFP/printer architectures utilizing packet-switched interconnect technology significantly increase the performance of peripheral devices while providing the benefits of reduced costs and quicker time to market for newly designed peripheral products.
In a specific implementation, an MFP device has an internal modular architecture which includes each of the main systems integrated onto separate ASIC (application specific integrated circuit) chips. Thus, a printer system, a scanner system, an input/output (IO) system, and a processor are each integrated onto separate ASIC chips. The systems are interconnected through a switch fabric which routes packet-based data between the systems based on destination addresses embedded in the packets. The packet-based data is routed between the switch fabric and each of the systems through switch IO buses which provide a dedicated, point-to-point connection between the switch fabric and each system.
In another implementation, the intra-system architecture of a printer device is similarly modularized to include its main functional systems each integrated onto separate ASIC chips. The printer system, an IO system, and a processor system are each integrated onto separate ASIC chips. The systems are coupled to one another through a switch fabric which routes packet-based data between the systems through switch 10 buses as described above.
An example of a packet-switched interconnect technology suitable for use with the modularized MFP/printer architectures described herein is the open standard RapidIO(trademark). RapidIO(trademark) is being developed and promoted as an open standard by the RapidIO(trademark) Trade Association. Other packet-switched interconnect technologies may also be suitable, such as the proprietary standard, Lightning Data Transport (LDT) being developed by Advanced Micro Devices.
The modular MFP/printer intra-system architectures using packet-switched interconnect technology are capable of data transfer rates in the gigabyte per second range. This is a significant performance advantage over prior MFP/printer architectures using conventional shared multi-drop buses, such as PCI (peripheral component interface), which have data transfer rates limited to a few megabytes per second. The modularized packet-switched architectures have lower transaction latency, higher bandwidth, and fewer pins per system than is possible using a shared bus architecture. Peripheral system functions in MFP and single peripheral/printer devices are implemented through separate ASIC systems which communicate through packet-based transactions and are connected through packet-switched interconnects that provide dedicated, point-to-point, and moderately parallel data paths.
Implementing peripheral functions through individual system ASICs has additional advantages in the production of MFP, peripheral, and printer devices. For example, the individual system ASICs are available for use across multiple product lines, rather than being limited to use in a specific peripheral product as is the case with highly integrated ASIC systems. In addition, minor design changes need only affect specific systems rather than requiring the redevelopment and reverification of an entire highly integrated ASIC.